Acrosser AR-B9612 Manuel d'utilisateur télécharger pdf (Page 24)

AR-B9612 User’s Guide

3-5

(3) I/O Channel Signal Description

Name Description

BUSCLK [Output]

The BUSCLK signal of the I/O channel is asynchronous to

the CPU clock.

RSTDRV [Output] This signal goes high during power-up, low line-

voltage or

hardware reset

SA0 - SA19

[Input / Output]

The System Address lines run from bit 0 to 19. They are

latched onto the falling edge of "BALE"

LA17 - LA23

[Input/Output]

The Unlatched Address line run from bit 17 to 23

SD0 - SD15

[Input/Output]

System Data bit 0 to 15

BALE [Output] The Buffered Address Latch Enable is used to latch SA0 -

SA19 onto the falling edge. This signal is forced high during

DMA cycles

-IOCHCK [Input] The I/O Channel Check

is an active low signal which

indicates that a parity error exist on the I/O board

IOCHRDY

[Input, Open collector]

This signal lengthens the I/O, or memory read/write cycle,

and should be held low with a valid address

IRQ 3-7, 9-

12, 14, 15

[Input]

The

Interrupt Request signal indicates I/O service request

attention. They are prioritized in the following sequence :

(Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest)

-IOR

[Input/Output]

The I/O Read signal is an active low signal which instructs

the I/O device to drive its data onto the data bus

-IOW [Input/Output]

The I/O write signal is an active low signal which instructs

the I/O device to read data from the data bus

-SMEMR [Output]

The System Memory Read is low while any of the low 1

mega bytes of memory are being used

-MEMR

[Input/Output]

The Memory Read signal is low while any memory location is

being read

-SMEMW [Output]

The System Memory Write is low while any of the low 1

mega bytes of memory is being written

-MEMW

[Input/Output]

he Memory Write signal is low while any memory location is

being written

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Acrosser AR-B9612 Manuel d'utilisateur Page 24

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